Here’s a number to sit with for a second: 0.7 nanometers.
On June 25, 2026, at the VLSI semiconductor symposium, IBM Research stood up and said it had built a chip on a 0.7-nanometer node — 7 angstroms, if you prefer the older unit physicists still like to use for things this small. They called it the smallest, most powerful chip technology in the world. And the moment you actually stop to think about what “0.7 nanometers” means, a very reasonable question should start forming in your head.
Because a single hydrogen atom is about 0.1 nanometers wide. Silicon atoms run a bit bigger, but not by much. So a “0.7 nanometer” chip feature would need to be — what, seven atoms across? Is IBM seriously telling us they’re building working transistors out of a handful of atoms lined up in a row?
Hold that question. It’s the right one to ask. And the answer is going to take us somewhere more interesting than a simple yes or no.
Wait — Is 0.7nm Actually the Size of Anything?
No. And IBM says so itself, in its own technical writeup, without being asked.
Here’s the quiet admission buried in IBM’s announcement: the “7 angstroms” in the node name doesn’t correspond to the width of any actual wire, gate, or feature on the chip — not anymore, and not for a while now. Decades ago, when chips were far less dense, a “90nm” or “65nm” process node really did roughly describe the size of the smallest transistor feature you could etch. But as the industry kept shrinking things and the marketing kept needing a smaller number to put on a slide, “node name” quietly detached from “physical measurement” and became something closer to a generational brand name — a bit like how a “4K” television doesn’t necessarily have exactly 4,000 horizontal pixels, or how a “size 10” shoe means different things at different stores. TSMC, Intel, and Samsung have all been playing the same naming game for over a decade; IBM just took it to its logical, slightly uncomfortable extreme.
So what’s actually true here? IBM has built a working chip with the smallest transistor features anyone has publicly demonstrated — full stop, that part is real and independently notable. It’s just that “0.7 nanometers” is doing more branding work than measuring work. Which raises the much better question.
Okay, So What Did IBM Actually Build?
Density. Absurd, category-breaking density.
The real headline number isn’t 0.7 — it’s 100,000,000,000. That’s roughly 100 billion transistors, packed onto a piece of silicon about the size of your fingernail. For comparison, a single human red blood cell is about 7,000 nanometers across — roughly 10,000 times larger than the individual transistor features IBM is now claiming. And this new chip packs nearly double the transistor density of IBM’s own 2-nanometer chip from 2021, which was itself the previous record holder.
Here’s the part that actually explains how they pulled that off, and it’s the real story: IBM didn’t get there by shrinking transistors sideways again. For sixty-plus years, the entire chip industry has played the same two-dimensional game — cram transistors closer together along the X and Y axes of a flat wafer. IBM’s engineers looked at that flat game board, decided it was basically full, and asked a different question: what if we stopped building outward and started building upward?
That’s the whole trick. It even has a name.
What Is a “Nanostack,” and Why Does Building Upward Even Help?
Picture a crowded city that’s run out of land. You don’t get more usable space by spreading the buildings further apart — you get it by building skyscrapers. IBM’s engineers are explicit about this exact metaphor: nanostack architecture is what happens when you stop treating a chip like a parking lot and start treating it like Manhattan.
Concretely: previous-generation chips (including IBM’s own 2021 “nanosheet” design, which itself replaced the older FinFET transistor style) arrange their two transistor types — called n-type and p-type, depending on how they’re chemically “doped” to control current flow — side by side on a flat plane. Nanostack architecture stacks them instead, one on top of the other, in a third dimension nobody had seriously unlocked for logic chips before. IBM Research director Nelson Felix put it plainly: the industry is running out of tricks for squeezing two different transistor materials closer together on a flat surface, so instead of fighting that wall, IBM went around it — vertically.
That single shift — stacking instead of squeezing — is what nearly doubles the transistor density without needing physically smaller components. But “just stack them” is doing a lot of hand-waving. Stacking two layers of working transistors on top of each other, with functioning wiring, without them interfering with or cooking each other, is a genuinely brutal engineering problem. So — how?
How Do You Even Stack Transistors Without It All Falling Apart?
Three real breakthroughs, and they’re each worth knowing, because each one solves a completely different flavor of “this shouldn’t work.”
Breakthrough one: wafer bonding thin enough to not ruin everything. To stack two layers of transistors, IBM had to bond two separate silicon wafers together into a single multilayered structure — and do it with a defect rate low enough that the resulting device actually functions as a true 3D transistor rather than a science project. The layers are joined through an ultra-thin dielectric bonding layer, engineered specifically to keep the wafers flat, aligned, and free of the kind of parasitic electrical interference that would otherwise turn “stacked transistors” into “expensive static noise.”
Breakthrough two: letting each transistor type have its own materials. Here’s a constraint that’s quietly shaped chip design forever: the ideal material for an n-type transistor isn’t the ideal material for a p-type transistor, but when they sit side by side on a flat wafer, you’re stuck compromising between them. Stack them instead, and — as IBM’s Tenko Yamashita explained — you can now choose completely different, independently optimized channel materials for each layer, in whichever order makes sense for the design. Decoupling those two transistor types from each other is arguably a bigger deal than the stacking itself.
Breakthrough three: moving power out of the way entirely. Normally, both power and data signals get routed through the front of a chip, competing for the same real estate. Nanostack chips flip that: power gets delivered from the back of the wafer instead, a technique called backside power delivery. Freeing up the front side for signal routing alone is a major reason IBM’s team was able to also boost on-chip memory (SRAM) density by 40% — a genuinely huge jump for chip memory, and one that directly attacks one of the biggest bottlenecks in AI computing: how fast a chip can access its own nearby memory.
None of this happened in a vacuum, either — which leads to a question most coverage of this story skipped entirely.
Who Else Had to Show Up to Make This Real?
This is the part of the story that turns a chip announcement into a geopolitics-of-technology story, and it’s worth pausing on.
Stacking transistors this precisely requires etching wires at a pitch tighter than 18 nanometers, arranged in a staggered, brick-like pattern between layers — a task that existing lithography tools genuinely cannot do reliably. IBM’s fix depends on equipment that doesn’t fully exist in production yet: High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography, built by the Dutch company ASML, which IBM is set to receive at its Albany NanoTech Complex in New York later this year. ASML’s own CEO, Christophe Fouquet, has confirmed the company was involved early specifically because nanostack needs the sharper resolution and tighter process control only High NA EUV can deliver.
That’s not the only outside partner in the room. California-based Lam Research is supplying a new dry EUV photoresist technology — replacing older wet-chemical processing methods — to improve yield and precision for exactly this kind of 3D structure. And Tokyo Electron, IBM’s semiconductor partner of more than two decades, is contributing its own lithography, etch, and bonding expertise to the effort. Put plainly: an American research lab, Dutch lithography, American process equipment, and Japanese manufacturing know-how all had to converge for this specific chip to exist. That’s the modern chip industry in miniature — no single country builds the cutting edge alone anymore, whatever the marketing slides suggest.
With all of that machinery finally assembled — what does it actually buy you?
Fine, But What’s the Actual Payoff?
This is where the numbers get genuinely aggressive, so let’s go through them straight.
Compared with IBM’s own 2021 2nm chip, the new nanostack design delivers roughly 50% more performance, or about 70% better energy efficiency, depending on which side of that trade-off a given chip design leans into. On the AI side specifically, IBM’s researchers estimate that an accelerator chip built on this 7-angstrom technology could hit around 9,000 trillion operations per second (TOPS) — roughly six times what today’s popular AI accelerator chips manage, at around 1,500 TOPS. Translate that into something concrete: IBM’s own estimate is that training a modern frontier-scale LLM, a process that currently takes around three months, could theoretically shrink to about two weeks on hardware built this way.
Add the 40% SRAM density gain from earlier, and you’re looking at a chip that’s not just faster in raw throughput but also less starved for nearby memory — which matters enormously for AI workloads, where waiting on memory access is often the actual bottleneck, not raw compute.
Which naturally leads to the question every reader is now itching to ask.
Can I Buy Anything With This Chip In It? (No. Here’s Why.)
None of this ships anywhere near you soon, and IBM isn’t pretending otherwise.
This is a research demonstration, not a product. No commercial manufacturing partner has been named for the nanostack process yet — a meaningful gap, since IBM Research doesn’t operate its own commercial fabs; its previous 2nm breakthrough, for example, had to be licensed out to manufacturing partners before it could reach real production lines. IBM’s own roadmap places widescale adoption of its current 2nm nanosheet chips toward the end of this decade, to be followed by 1.4nm and then 1nm nanosheet-based nodes — and only after all of that does nanostack architecture take over as the production standard. IBM expects nanostack technology to power chip design for more than a decade once it does arrive, potentially extending logic scaling all the way out to 2040. But “start of that decade-long run” and “today” are not the same thing.
Context helps here too: TSMC is already shipping 2nm chips in volume production right now, and Intel’s 1.8nm-class 18A-P process entered risk production back in June 2026. IBM’s 0.7nm demonstration is, on paper, roughly two full node generations ahead of what either competitor is currently shipping — but “ahead on a research bench” and “ahead in your laptop” are very different races, and IBM has a well-established habit of winning the first one by years before the second one catches up.
The Honest Skeptic’s Corner
Is any of this hype? Only partially, and it’s worth being precise about which part.
The engineering itself isn’t vague roadmap talk — IBM showed actual transmission electron microscope imagery of working stacked transistors, named the specific scientists and technical leads behind each breakthrough, and lined up three real external manufacturing partners (ASML, Lam Research, Tokyo Electron) who don’t attach their names to vaporware. That’s a meaningfully higher bar of evidence than most “breakthrough chip” press releases clear.
What’s fair to be skeptical about is the timeline, not the physics. IBM announced its 2nm breakthrough with similar fanfare back in 2021; five years later, in 2026, 2nm chips are only just reaching wide commercial availability through other companies’ fabs. If that pattern holds, “0.7nm” chips reaching an actual product you can buy is realistically a story for the early-to-mid 2030s, not next year’s flagship phone. IBM itself all but says as much by pointing to a roadmap with two more full node generations scheduled before nanostack becomes the production standard.
So Where Does This Actually Leave Us?
Back to that opening number, one more time. 0.7 nanometers — 7 angstroms — genuinely does approach the physical diameter of just a few atoms strung together. IBM’s own scientists don’t dodge that; they simply point out that when you can’t meaningfully get smaller, you can still get taller, and you can still get smarter about materials. That reframing — from “how small can we make it” to “how many dimensions can we use” — is the actual breakthrough hiding underneath the eye-catching 0.7 number. The node name was always going to be the least interesting part of this story. The city IBM built on top of a fingernail-sized plot of silicon is the part worth remembering.
FAQ
Is IBM’s 0.7nm chip actually 0.7 nanometers wide? No single feature on the chip literally measures 0.7 nanometers — IBM acknowledges the node name is a branding convention rather than a physical measurement, a practice the whole chip industry adopted years ago as feature sizes shrank past the point where the old naming made literal sense.
What is nanostack architecture? It’s IBM’s new 3D transistor design that stacks n-type and p-type transistors vertically instead of placing them side by side on a flat wafer, roughly doubling transistor density without shrinking individual components further.
How many transistors does the new chip have? Roughly 100 billion transistors on a piece of silicon about the size of a fingernail.
When will chips using this technology be available to buy? Not soon. No manufacturing partner has been announced, and IBM’s own roadmap places two more full node generations (1.4nm and 1nm, on its current nanosheet architecture) ahead of nanostack becoming the production standard, likely placing real commercial availability in the early-to-mid 2030s.
How does this compare to what TSMC and Intel are currently shipping? TSMC is currently mass-producing 2nm chips, and Intel’s 1.8nm-class 18A-P process entered risk production in mid-2026. IBM’s 0.7nm nanostack chip is a research demonstration roughly two node generations ahead of both on paper, but years from commercial production.
Why does this matter for AI specifically? IBM estimates AI accelerator chips built on this technology could deliver around six times the raw compute of today’s chips, plus a 40% increase in on-chip memory density — directly addressing the memory-bandwidth bottleneck that slows down large AI model training and inference today.
